The Joy of Hardware Manifesto 🚀

The chip-design world is broken. Not in the obvious, dystopian way that movies like to depict—but in the more insidious way that stifles progress while pretending everything is fine.

The industry is drowning in bad tools, bad processes, and bad incentives that hold back innovation.

💡 If we don't build a better way, it will never exist.

What is The Joy of Hardware?

The Joy of Hardware (JOH) is not just a platform. It's a movement.

JOH exists to make learning and building hardware actually enjoyable.

JOH exists to obliterate the pain of bad tools starting with FPGA design, where vendor lock-in, broken workflows, and archaic methodologies waste thousands of engineering hours.

JOH exists to accelerate the next generation of engineers by giving them the tools and workflows that should have existed all along.

By fixing FPGA workflows first, we lay the foundations to hopefully move up the stack to reshape EDA as a whole.

The Problems We're Fixing Right Now

1️⃣ Bye-bye bad tools!

2️⃣ Comprehensive Hardware Educational Content is Sparse

We're working on world class tutorials that teach you from the ground up:

3️⃣ Everything Should Be Reproducible - No More “Works on My Machine”

We are fixing this with Nix.

NixOS for RISC-V softcores, fully reproducible.

Every project, every example, and every IP block will have a Nix flake, ensuring perfect builds every time.

4️⃣ FPGA Development in Your Browser—No Setup Required

Yes, you read that right. Our in-browser IDE will let you write, compile, and program hardware without ever leaving your browser.

We've ported OpenFPGALoader to work via WebUSB, meaning you can flash your FPGA directly from the IDE—no extra software required.

Imagine writing Bluespec, compiling your design, and flashing your FPGA—all from a single, seamless web-based environment.

The Plan

🔥 Phase 1: Fix FPGA Design 🔥

Start with FPGAs because they’re the fastest path to innovation, widely available, cheap to prototype, and unshackled from the long lead times of chip fabrication.

🚀 Phase 2: Fix Chip Design 🚀

Next, we go deeper—moving beyond FPGA design into full-stack chip development. From RTL to GDSII, our mission is to redefine silicon design with the same rigor we bring to FPGAs.

🚀 Why We Have to Do This

Because nobody else will.

Because corporate R&D is too slow, too risk-averse, and too locked into bad systems.

Because if we don't build better hardware tooling, we will forever be stuck in the past.

💻 Browse The Code

There's still a lot of work to do, but we believe in full transparency. Explore our repositories and check our progress.

Explore the Code

🔥 Join Us. 🔥